Simplescalar Installation
Simple Scalar Installation Tips
Files Needed :
simpletools-2v0.tgz& from
simplesim-3vd.tgz& from&
simpleutils-2v0.tgz& from
gcc-2.7.2.3.ss.tar.gz& from
May need : ar& from
May need : ranlib& from
Installation Instructions :
the steps below. Common problems encountered during installation are
listed. These should be sufficient to install simplescalar successfully
the GCL machines (recent Ubuntu). In case simplescalar throws new
errors at you, please mage Google search your friend.
Find the basics of the system you are working on.
Use following command to check if it's a 64-bit system :
If it is a 64-bit system, it might need some changes in the
installation procedure.
Unzip all the installation files. Delete the folder gcc-2.6.3
Create the folder where you want to install simplescalar. Move all the
uncompressed installation files into it.
Set environment variables as follows:
export IDIR=&your-simplesclar-installation-dir&
export HOST=i686-pc-linux
export TARGET=sslittle-na-sstrix
Ensure required dependencies are installed. You would need build-essential, flex, bison.
In some systems, an error of the sort of "cannot find output from lex"
may be thrown in spite of flex being installed.
Come around this by creating a symbolic link :
ln -s /usr/local/bin/flex-2.5.4 flex
doing this after seeing an error in the next step, remove current
simpleutils directory & restart Step 3 with a freshly
uncompressed
copy. In some extreme cases, this would get reflected only after a
Install SimpleUtils
cd $IDIR/simpleutils-990811
Fix these errors in the source :
Find yy_current_buffer
in the file ld/ldlex.l
& replace it with YY_CURRENT_BUFFER
. (If this is not done, an error of "`yy_current_buffer' undeclared"
would be thrown)
Execute following commands to complete installing :
./configure --host=$HOST --target=$TARGET --with-gnu-as --with-gnu-ld
--prefix=$IDIR
make CFLAGS=-O
make install
Install the simulators
cd $IDIR/simplesim-3.0
make config-pisa
This should work without any errors. Test
./sim-safe tests/bin.little/test-math
Install gcc cross-compiler
cd $IDIR/gcc-2.7.2.3
./configure --host=$HOST --target=$TARGET --with-gnu-as --with-gnu-ld
--prefix=$IDIR
chmod -R +w .
Fix these errors in the source :
line#60 of file protoize.c,
replace "#include
&varargs.h&" with
"#include&stdarg.h&"
(To avoid error claiming GCC no longer
implements varargs.h)
In line#341 of file decl.c
obstack.h,
**)__o-&next_free)++ = ((void *)datum);\" with "*((void
**)__o-&next_free++)=((void *)datum);\"
&(To avoid error saying
something about "invalid lvalue in increment in function
push_class_level_binding"
Comment out lines
in file cxxmain.c (To avoid
error that says malloc & realloc have already been declared)
./patched/sys/cdefs.h ../sslittle-na-sstrix/include/sys/cdefs.h
&(To avoid error looking like "Fix these errors in the source
../sslittle-na-sstrix/lib/libc.a ../lib/
../sslittle-na-sstrix/lib/crt0.o ../lib/
Copy files ar & ranlib into $IDIR/sslittle-na-sstrix/bin
(To avoid "buffer overflow" error involving ar or ranlib)
[The last three may not be needed in some systems. But are needed in
the latest Ubuntu systems].
make LANGUAGES=c CFLAGS=-O CC="gcc -m32"
This should throw an error : "insn-output.c:xyz: missing terminating "
character".
Insert \ at the end of lines 675, 750 & 823 of file insn-output.c. The
lines should look like "return
"FIXME\n\"
make LANGUAGES=c CFLAGS=-O CC="gcc -m32"
make enquire
$IDIR/simplesim-3.0/sim-safe ./enquire -f & float.h-cross
make LANGUAGES=c CFLAGS=-O CC="gcc -m32" install
In the GCL machines, that should see you through. Other problems that
you are likely to encounter are below :
If it's a 64-bit OS, you might need to use CC="gcc -m64" or CC="gcc" in the
above make commands. Otherwise, it complains that "stubs-64.h" isn't
If the error looks like "&path&/stdio.h:167:
parse error before `void'", try editing Makefile at line#130
& append -I/usr/include
to the end of that line.
For error about "libgcc2.c:484: `BITS_PER_UNIT'
undeclared", change line#97 of file libgcc2.c
to "#define
BITS_PER_UNIT 8"
For "sendmsg.c:36: parse error", in file objc/sendmsg.c,
insert "#define
INVISIBLE_STRUCT_RETURN 0" at line 35, and delete lines 36
to 40 (inclusive).
Try it out. Simplescalar is installed now.
In a new directory, create a simple hello world C program - hello.c
Compile it using the cross-compiler with the following command :
$IDIR/bin/sslittle-na-sstrix-gcc -o hello hello.c
Run it using a simulator :
$IDIR/simplesim-3.0/sim-safe hello
You should see some statistics after the lines "sim: **starting
functional simulation** Hello World!" as the output.
you want to really relax, try adding the simplescalar simulator
cross-compiler directories to your PATH so as to avoid typing the
entire path each time :
export PATH=$PATH:$IDIR/bin/:$IDIR/simplesim-3.0Add this line to your ~/.bashrc filegem5源代码文件结构作用介绍
下面介绍了gem5目录结构中各个文件的作用
Read the SConscript file before reading other files because this will give you an understanding of how
the files are linked to each other.
./build_opts/
Few files which set some variables used when building gem5. There is a file each for each ISA and each memory model
./configs/boot/
RCS scripts mainly used for running benchmarks in FS mode. It covers all the SPEC benchmarks
./configs/common/
Benchmarks.py
Configuration script used for running benchmarks in FS mode. It will set the SysConfiguration.
SysConfig Class which contains scriptname, diskname and memsize. The disk containing benchmarks
can be specified in this file for each ISA.
Benchmarks are defined as a key in a dict which is a list of SysConfigs
The first defined machine is the test system, the others are driving systems
Different SysConfigs are defined for different benchmarks - by setting the script, memsize
The scripts are located in ./configs/boot
CacheConfig.py
Configures the cache system for the system being simulated. Based on the command line
options given when gem5.opt is run, it creates the cache configuration to be used
Defines default parameters of L1, L2, IO, PageTableWalker Cache
CPUConfig.py
Builds the list of available CPU models and checks whether the option given on command line is an available CPU
FSConfig.py
Creates the different CPU models( MIPS, ALPHA, SPARC, etc.) for Full System simulation
Address Ports, Memory Busses etc.
O3ARMv7a.py
Defines the configuration parameters of ARMv7 CPU model. Various Functional Units, Branch Predictors, LSQs, caches, TLBs, etc.
All classes derive from generic clasess used in basic O3 model
Options.py
Defines all the command line options like -cpu-type, -cpu-number etc.
system options, run duration options, checkpointing options, Fastforwarding and simpoint related materials, Benchmark options,
FS options
Simulation.py
CPU models for restoring from checkpoint, initial fast-forwarding
Defines functions to set the simulation configuration like max time, fast-forward or detailed, creating checkpoints, restoring from checkpoints,
Switching CPUs, Actual Run after setting all these options, different types of switching are possible
SysPaths.py
Configures the paths for disks file, script file etc.
cpu2000.py
Configuration file for running SPEC2000 benchmarks
./config/examples
Script to run FS simulation. Takes command line options and retrieves required information. Imports files from ./config/common
Similar files for testing memory system, running in SE mode. All of these import the files present in ./config/common
./config/ruby
Scripts related to ruby memory system
./config/splash2
cluster.py
Configuration related to running splash2 parallel benchmarks
Defines a class for each splash2 benchmark which inherits from LiveProcess class
Each class contains info about executable, cmd, input variables
Defines cache structure, number and type of clusters and number of cpus in a cluster - all obtained from command-line options
Creates a system, adds system-wide objects, connects them. Picks the correct benchmark, assigns the workload ans runs the simulation
Same as cluster.py with minor changes - clusters are not present
./config/topologies
Topologies for memory controllers
Low level software like firmware or bootloaders for use in simulated systems.
alpha - Alpha console and palcode.
arm - A simple ARM bootloader.
./src/base/
Defines global host-dependent types:
Counter, Tick, and (indirectly) {int,uint}{8,16,32,64}_t.
Cycles class, Addr, MicroPC, MicroPC operations,
Defines flag class, functions for modifying flags like set, unset etc.
Handles printing of data to an output stream
./src/base/stats/
Namespace Stats- Defines some basic stats types like Counter, VCounter, Result
Info class to store information about various types of Stat like name, desc.
For Distributions, 2d-Vectors etc. we store min_val, max_val etc.
output.hh, text.hh, text.cc Printing of stats to output stream
./src/base/vnc/
VncInput class which derives from SimObject class
VncServer class which derives from VncInput
Some files related to handling input to vncserver and setting up
a vncserver
./src/base/loader/
object_file.hh
Class Object File - Architecture, OS. Mainly deals with how to read data from an object file
All files in this folder provide some classes which can be used to read various types of object files
RefCounted and RefCountingPtr classes which enable a class to be reference counted and provide automatic
reference counting respectively.
./src/arch/generic/
Generic classes which can be used to perform specific functions using any ISA like decode_cache, debug_fualts, memhelpers.hh
./src/arch/arm/
Classes which define what each instruction will do and to access information about instructions like branch, mem, misc, mult, etc.
.isa files which define how to decode an arm.thumb instruction
.isa files which define various instruction formats like m5ops, branch, mem, etc.
Declarations of execution methods used for different types
PYTHON FOLDER
./m5/util/convert - Functions to convert a given string to numerical values related to memory size, clock period, network bandwidth etc.
./m5/util/attrdict - Modified Dict types with capability to add and delete attributes and a heirarchical structure
./m5/util/multidict - Dict of Dict and so on
./m5/util/orderdict - Ordered Dict
./m5/util/smartdict - Dictionary class that holds strings, but intelligently converts those strings to other types depending on their usage
./m5/util/sortedict -
./m5/util/region - Places data in regions and determines the type of overlap between two regions
./m5/util/init - Defines the error calls - panic, fatal, warn and inform. Several other utility functions
./m5/internal/params.py - A simple function to load all modules starting with m5.internal.params
./m5/internal/init - Imports some modules used in the simulator like core, event, stats, etc.
./m5/objects/init - Imports all modules starting with m5.objects
./m5/config.py - Directory settings for m5
./m5/debug.py - Extracting debug flags from m5 and printing them
./m5/event.py - Defines Event and Progress Event classes and related functions
./m5/main.py - The main script invoked when gem5 is run. Option parsing, gem5 interactive console , main function which prints info while gem5 is running
./m5/options.py Option parser
./m5/params.py - Parameter description classes. Each class has a _params dictionary which maps parameter names to Param objects. Functions which generate C++ code
needed as a pre-requisite for declaring certain C++ objects. Defines several functions which deal with parameters
./m5/proxy.py - Proxy object support
./m5/ticks.py - Setting simulation accuracy and global frequency
./m5/SimObject.py -
./m5/simulate.py - Functions to instantiate Simobjects used in the system, create checkpoints, restore from checkpoints, switch cpus etc.
In short, this script is responsible for starting and ending a simulation
./m5/stats/init - Initialization, resetting, dumping, et. of statistics
Swig files for the main module defined in m5
SIMULATION FOLDER
./arguments.hh
Class arguments which has a thread context, number, data and methods which change or compare number field
./async.hh
Defines flags used to handle asynchronous simulator events
./byteswap.hh
Provides endianness coversion utility functions
./clocked_object.hh
The ClockedObject class extends the SimObject with a clock and accessor functions to relate ticks to the cycles of the object.
Core simulator functionality such as time information, output directory and exit events. Few simple functions
./eventq.hh
Class Event derives from Serializable and is a friend of class EventQueue. EventQueueManager
./serialize.hh
Serialization interface declarations
./debug.hh
Provides the definitions for some useful debugging functions. These are intended to be called from a debugger such as gdb
./drain.hh
Coordinates draining of a system. Drainable class. Functions to perform draining
./faults.hh
Various types of faults, their names and invoking functions.
EmbeddedPython, EmbeddedSwig structs. Some initialization function and handler functions
./insttracer.hh
Class InstRecord. Class InstTracer which mostly derives from SimObject
./microcoderom.hh
Generic stub microcode ROM ISAs can use if they don’t need anything more
Sets up python and then calls initM5Python which loads the various embedded python modules
into the python environment and then starts things running by calling m5Main.
./syscallreturn.hh
Class SyscallReturn. Successful and retval fields
./process.hh
All the details that are related to a process running on a cpu
class Process deriving from SimObject
class LiveProcess deriving from Process
./pseudo_inst.hh
PseudoInst namespace which defines several functions which behave like instructions and
perform several operations on a ThreadContext
The root SimObject in the simulation hierarchy
serialize.hh
Functions to create and restore from checkpoints
Serialize - create checkpoints Unserialize - Restore from checkpoints
./sim_events.hh
Event to terminate simulation at a particular cycle/instruction
CountedDrainEvent, CountedExitEvent
Used to terminate simulation after some special event
./sim_exit.hh
Functions which return the control to python after ending simulation
./sim_object.hh
Abstract superclass for simulation objects. Represents things that
correspond to physical components and can be specified via the
config file (CPUs, caches, etc.).
Methods used in starting and running a simulation
./simulate.hh
simulate method which returns SimLoopExitEvent
./stat_control.hh
Events related to dumping, resetting and registering statistics
./syscall_emul.hh
Defines objects used to emulate syscalls from the target
application on the host machine.
./syscallreturn.hh
SysCallReturn Class which decodes the return value of a system call
./system.hh
Classes which define the system, ports, connections between system components
BaseTLB and GenericTLB classes
./src/cpu/
timebuf.hh
TimeBuffer and Wire classes. Friends of each other. Wire contains TimeBuffer
Used for sending data between two objects
activity.hh
Activity Recorder helper class that informs the CPU if it can switch over to being idle or not
CPUProgressEvent deriving from Event
BaseCPU deriving from MemObject
cpuevent.hh
CpuEvent class- Helps form a global list of events which need a pointer to a ThreadContext
decodecache.hh
Cache of recent Virtual Memory decodings and retrieval mechanisms from cache
exec_context.hh
ExecContext - Not a usable class. Only to demonstrate how ISA accesses CPU state
FuDesc and OpDesc classes which define a functional unit and its operations.
inst_seq.hh
Used to order instructions in the ready list
static_inst.hh
StaticInst class - Machine Inst, Flags, OpClass, Num of Src, Dest regs, Flag Accessor Functions
thread_context.hh
ThreadContext Class Accessor and Modifier functions for all registers, memory ports and most of the
architectural state of a CPU. It is a virtual class.
So, we make use of ProxyThreadContext class to prevent the overhead of virtual callprevent the overhead of virtual calls
profile.hh
ProfileNode and FunctionProfile classes
thread_state.hh
Struct for holding general thread state that is needed across CPU models.
Very similar to thread_context with minor changes
Changing the thread state and priority for smt support
translation.hh
Captures the state of an address translation
WholeTranslationState and DataTranslation Classes
exectrace.hh
ExeTraceRecord and ExeTracer classes
simple_thread.hh
The SimpleThread object provides a combination of the ThreadState
object and the ThreadContext interface
quiesce_event.hh
EndQuiesceEvent for timing out a quiesce instruction
intr_control.hh
Class to clear and post instructions of a particular CPU
legiontrace.hh
LegionTraceRecord and LegionTrace
pc_event.hh
PCEventQueue class which contains PCEvent class objects
base_dyn_inst.hh
Defines a dynamic instruction context
All the functions and processes that happen in a simple processor
are defined in this class. Including functions for writing, reading memory,
starting and ending translation etc.
Python Files
These files define the Python Objects, methods, files which point to the
corresponding C++ object, using Cxx header and Cxx class variables
./src/cpu/checker/
thread_context.hh
Derived ThreadContext class for use with the Checker. The template
parameter is the ThreadContext class used by the specific CPU being
verified. This CheckerThreadContext is then used by the main CPU in
place of its usual ThreadContext class. It handles updating the
checker’s state any time state is updated externally through the
ThreadContext.
CheckerThreadContext - Actual Thread Context, Checker Thread, Checker CPU
CheckerCPU class derives from BaseCPU class.
BaseCPU is an abstract class. So CheckerCPU
has most of the methods and members replicated
Templated Checker Class deriving from CheckerCPU
which handles the checking/verifying functions
cpu_impl.hh
./src/cpu/simple
BaseSimpleCPU derives from BaseCPU
CheckPcEventQueue - Seems to be the main function
which moves instructions forward
Lots of stats variables
AtomicSimpleCPU derives from BaseSimpleCPU
TickEvent Struct containing a CPU, TickEvent, Process methods
Main simulation loop - tick method
Class SplitMainSenderState to split memory access into two fragments
It has some TLB and memory access functions in addition to
Atomic functionality
./src/cpu/pred
DefaultTLB class
Very simple and straight forward implementation of BTB
ReturnAddrStack class
sat_counter.hh
Private counter class for the internal saturating counters.
Implements an n bit saturating counter and provides methods to
increment, decrement, and read it
bpred_unit.hh
Wrapper class to hold both the Branch Predictor and BTB
Predictor Histroy Struct to maintain information required to
update BTB, RAS etc.
tournament.hh
Implements a tournament branch predictor
TournamentBP inherits from BPredUnit
2bit_local.hh
Implements a local predictor that uses the PC to index into a table of
counters. Contains a list of saturating counters.
OUT OF ORDER
./src/cpu/o3/
base_dyn_inst.cc
Makes an explicit instantiation of BaseDynInst templated class with
checker.hh
Specific non-templated O3Checker derived class used for SimObject configuration.
Structures that define the information passed on from one stage to another stage of
a superscalar pipeline
Each struct contains a list of DynInstPtr
Per thread variable like branchmisPredict, branchTaken etc.
A special structure which defines all backward communication - TimeBufStruct
Templated DefaultCommit Class
Has pointers to all the important structures and stages in the CPU
All the important architectural updates are handled
Because instructions are actually decoded when the StaticInst is created,
this stage does not do much other than check any PC-relative branches
DefaultDecode - Very similar to DefaultCommit class
dep_graph.hh
Array of linked list that maintains the dependencies between
producing instructions and consuming instructions
dyn_inst.hh
BaseO3DynInst deriving from BaseDynInst
DefaultFetch Class
free_list.hh
SimpleFreeList class that simply holds the list of free integer and floating
point registers.
fu_pool.hh
FUPool class which maintains a list of arrays of FUunits with a specific
Capability
Implementation specific struct that defines several key types to the
CPU, the stages within the CPU, the time buffers, and the DynInst.
inst_queue.hh
Instruction Queue which holds and schedules intructions
Gets information from FUs and MemUnit to track dependencies and
resource availability
lsq_unit.hh
LSQUnit Class which implements Load and Store Queues
LSQ class Templated with Impl
mem_dep_unit.hh
Memory Dependency Predictor
regfile.hh
Simple physical register file class.
Methods to set and read int and fp registers
scoreboard.hh
Implements a simple scoreboard to track which registers are ready
ROB class. The ROB is largely what drives squashing.
DefaultRename Class which handles both single threaded and SMT rename
thread_context.hh
Derived ThreadContext for use with O3CPU
thread_state.hh
O3ThreadState class that has various thread state, such as the status, the
current instruction being processed, whether or not the thread has
a trap pending or is being externally updated, the ThreadContext
pointer, etc.
store_set.hh
Implements a store set predictor for determining if memory insts
are dependent on each other
DeriveO3CPU derived from templated FullO3CPU
DefaultIEW class which implements the iew stage of the pipeline
cpu_policy.hh
SimpleCPUPolicy Struct that defines the key classes to be used by the CPU.
All classes use the typedefs defined here to determine what are the
classes of the other stages and communication buffers.
BaseO3CPU deriving from BaseCPU
FullO3CPU deriving from BaseO3CPU
FullO3CPU class has each of the stages (fetch through commit)
within it, as well as all of the time buffers between stages.
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