>> altera_tse_altgx_civgx_gige.v
altera_tse_altgx_civgx_gige.v ( 文件浏览 )
// megafunction wizard: %ALTGX%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: alt_c3gxb
// ============================================================
// File Name: altera_tse_altgx_civgx_gige.v
// Megafunction Name(s):
// Simulation Library Files(s):
altera_cycloneiv_hssi
// ============================================================
// ************************************************************
// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
// 12.0 Internal Build 147 03/05/2012 PN Full Version
// ************************************************************
//Copyright (C)
Altera Corporation
//Your use of Altera Corporation's design tools, logic functions
//and other software and tools, and its AMPP partner logic
//functions, and any output files from any of the foregoing
//(including device programming or simulation files), and any
//associated documentation or information are expressly subject
//to the terms and conditions of the Altera Program License
//Subscription Agreement, Altera MegaCore Function License
//Agreement, or other applicable license agreement, including,
//without limitation, that your use is for the sole purpose of
//programming logic devices manufactured by Altera and sold by
//Altera or its authorized distributors.
Please refer to the
//applicable agreement for further details.
//alt_c3gxb CBX_AUTO_BLACKBOX=&ALL& device_family=&Cyclone IV GX& effective_data_rate=&1250.0 Mbps& equalization_setting=1 equalizer_dcgain_setting=0 gxb_powerdown_width=1 loopback_mode=&none& number_of_channels=1 number_of_quads=1 operation_mode=&duplex& pll_bandwidth_type=&high& pll_control_width=1 pll_divide_by=&1& pll_inclk_period=8000 pll_multiply_by=&5& pll_pfd_fb_mode=&internal& preemphasis_ctrl_1stposttap_setting=1 protocol=&gige& receiver_termination=&OCT_100_OHMS& reconfig_calibration=&true& reconfig_dprio_mode=0 reconfig_pll_control_width=1 rx_8b_10b_mode=&normal& rx_align_pattern=&1111100& rx_align_pattern_length=7 rx_allow_align_polarity_inversion=&false& rx_allow_pipe_polarity_inversion=&false& rx_bitslip_enable=&false& rx_byte_ordering_mode=&none& rx_channel_width=8 rx_common_mode=&0.82v& rx_datapath_protocol=&basic& rx_deskew_pattern=&0& rx_digitalreset_port_width=1 rx_dwidth_factor=1 rx_enable_bit_reversal=&false& rx_enable_lock_to_data_sig=&false& rx_enable_lock_to_refclk_sig=&false& rx_enable_second_order_loop=&false& rx_enable_self_test_mode=&false& rx_force_signal_detect=&true& rx_loop_1_digital_filter=8 rx_ppmselect=8 rx_rate_match_fifo_mode=&normal& rx_rate_match_fifo_mode_manual_control=&normal& rx_rate_match_pattern1=&& rx_rate_match_pattern2=&& rx_rate_match_pattern_size=20 rx_run_length=5 rx_run_length_enable=&true& rx_signal_detect_loss_threshold=1 rx_signal_detect_threshold=8 rx_signal_detect_valid_threshold=14 rx_use_align_state_machine=&true& rx_use_clkout=&true& rx_use_coreclk=&false& rx_use_deskew_fifo=&false& rx_use_double_data_mode=&false& rx_use_external_termination=&false& rx_word_aligner_num_byte=1 starting_channel_number=0 top_module_name=&altera_tse_altgx_civgx_gige& transmitter_termination=&OCT_100_OHMS& tx_8b_10b_mode=&normal& tx_allow_polarity_inversion=&false& tx_bitslip_enable=&false& tx_channel_width=8 tx_clkout_width=1 tx_common_mode=&0.65v& tx_digitalreset_port_width=1 tx_dwidth_factor=1 tx_enable_bit_reversal=&false& tx_enable_self_test_mode=&false& tx_slew_rate=&medium& tx_transmit_protocol=&basic& tx_use_coreclk=&false& tx_use_double_data_mode=&false& tx_use_external_termination=&false& use_calibration_block=&true& vod_ctrl_setting=1 cal_blk_clk fixedclk fixedclk_fast gxb_powerdown pll_areset pll_inclk pll_locked reconfig_clk reconfig_fromgxb reconfig_togxb rx_analogreset rx_clkout rx_ctrldetect rx_datain rx_dataout rx_digitalreset rx_disperr rx_errdetect rx_freqlocked rx_patterndetect rx_recovclkout rx_rlv rx_rmfifodatadeleted rx_rmfifodatainserted rx_runningdisp rx_syncstatus tx_clkout tx_ctrlenable tx_datain tx_dataout tx_digitalreset intended_device_family=&Cyclone IV GX&
//VERSION_BEGIN 12.0 cbx_alt_c3gxb :21:09:17:PN cbx_altclkbuf :21:09:17:PN cbx_altiobuf_bidir :21:09:17:PN cbx_altiobuf_in :21:09:17:PN cbx_altiobuf_out :21:09:17:PN cbx_altpll :21:09:17:PN cbx_cycloneii :21:09:17:PN cbx_lpm_add_sub :21:09:17:PN cbx_lpm_compare :21:09:17:PN cbx_lpm_counter :21:09:17:PN cbx_lpm_decode :21:09:17:PN cbx_lpm_mux :21:09:17:PN cbx_mgl :22:13:55:PN cbx_stingray :21:09:16:PN cbx_stratix :21:09:18:PN cbx_stratixii :21:09:18:PN cbx_stratixiii :21:09:18:PN cbx_stratixv :21:09:18:PN cbx_util_mgl :21:09:17:PN
VERSION_END
// synthesis VERILOG_INPUT_VERSION VERILOG_2001
// altera message_off 10463
//synthesis_resources = altpll 1 cycloneiv_hssi_calibration_block 1 cycloneiv_hssi_cmu 1 cycloneiv_hssi_rx_pcs 1 cycloneiv_hssi_rx_pma 1 cycloneiv_hssi_tx_pcs 1 cycloneiv_hssi_tx_pma 1 reg 3
//synopsys translate_off
`timescale 1 ps / 1 ps
//synopsys translate_on
(* ALTERA_ATTRIBUTE = {
&suppress_da_rule_internal=c104&
altera_tse_altgx_civgx_gige_alt_c3gxb_g308
cal_blk_clk,
fixedclk_fast,
gxb_powerdown,
pll_areset,
pll_inclk,
pll_locked,
reconfig_clk,
reconfig_fromgxb,
reconfig_togxb,
rx_analogreset,
rx_clkout,
rx_ctrldetect,
rx_datain,
rx_dataout,
rx_digitalreset,
rx_disperr,
rx_errdetect,
rx_freqlocked,
rx_patterndetect,
rx_recovclkout,
rx_rmfifodatadeleted,
rx_rmfifodatainserted,
rx_runningdisp,
rx_syncstatus,
tx_clkout,
tx_ctrlenable,
tx_datain,
tx_dataout,
tx_digitalreset) /* synthesis synthesis_clearbox=2 */;
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_off
`ifndef ALTERA_RESERVED_QIS
// synopsys translate_on
parameter starting_channel_number = 0;
wire_pll0_
wire_pll0_
wire_pll0_
wire_pll0_
wire_cal_blk0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_cent_unit0_
wire_receive_pcs0_cd
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pcs0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_receive_pma0_
wire_transmit_pcs0_
wire_transmit_pcs0_
wire_transmit_pcs0_
wire_transmit_pcs0_
wire_transmit_pma0_
wire_transmit_pma0_
wire_transmit_pma0_
wire_transmit_pma0_
reg [0:0] fixedclk_
reg [1:0] reconfig_togxb_busy_
wire cal_blk_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_tx_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
cent_unit_
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4.96 kB 21:21
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eth_std_main_system_ethernet_subsystem_tse_mac_constraints.sdc34.52 kB 21:20
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